Processor technology is the cornerstone of digitalization, from smartphones, computers, servers, to automobiles, industrial control, and medical devices; almost all electronic devices require processors to operate. Processors act like brains, directing the operation of devices, processing information, and executing instructions.
Among the many processor architectures, RISC-V, with its open-source nature, concise instruction set, and scalability, is regarded by the industry as an important contender for the next generation of processor architectures, bringing new vitality to the processor market.
Introduction to RISC-V
RISC-V initially started as a project at the University of California, Berkeley, aimed at creating an open-source computer system based on RISC principles, initially designed for academic purposes. With the evolution of the standard, RISC-V is now managed by RISC-V International. To maintain the neutrality of global designers and avoid interference from any government regulations, RISC-V International has relocated its headquarters to Switzerland. Currently, the RISC-V ecosystem is gradually taking shape and developing to support this standard. With the acceleration of adoption rates and ongoing industry collaboration, the architecture is further evolving.
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RISC-V is widely popular due to the simplified instructions provided by its architecture, which can help processors perform various tasks; designers can leverage RISC-V to create thousands of potential custom processors to speed up product time-to-market; the universality of processor IP also saves software development time. In addition to this, RISC-V has many advantages: its open standard feature allows for full cooperation and innovation within the industry; the universal ISA makes software development easier because all processors can use the same architecture; designers can use the same basic ISA to customize devices from simple embedded devices to the largest supercomputers according to market demand; compared to previous ISAs, the RISC-V ISA has unique features and can be customized according to needs; it offers smaller, more energy-efficient modular options; security features provided through open-source reference designs, software composition analysis tools, and security extensions; moreover, its open-source nature means the entire RISC-V architecture can be scrutinized in the public domain, eliminating backdoors and hidden channels.
Full-stack Support for RISC-V
In November last year, Synopsys expanded its ARC processor product portfolio by incorporating the RISC-V processor series, launching a brand-new ARC-V processor IP series. As a leading semiconductor EDA/IP supplier in the industry, Synopsys is actively positioning itself in the RISC-V market against the backdrop of the booming RISC-V architecture, aiming to create new development opportunities for current and future customers as well as the entire ecosystem.
Synopsys provides extensive implementation and verification support for the growing RISC-V market. This strategy covers architecture exploration, IP support, software development, DevOps, HW/SW verification, design service providers, and various simulation and verification methods.
The ARC-V processor IP is based on the open standard RISC-V Instruction Set Architecture (ISA), allowing customers to access the evolving RISC-V ecosystem. Currently, Synopsys's ARC processor IP product portfolio includes processors based on ARC-V RISC-V, verified 32/64-bit CPU IP, DSP IP, Neural Network Processing Unit (NPU) IP, subsystems, and software development tools.Synopsys' ARC-V processor IP includes high-performance, mid-range, and ultra-low power RISC-V processor options as well as functional safety versions, providing the best power-performance efficiency for a wide range of application workloads. The ARC-V product portfolio is built on the successful foundation of multiple generations of ARC processor IP, covering a wide range of processor implementations, including functional safety (FS) versions, offering everything needed for optimized and differentiated SoC.
In terms of ARC/ARC-V cores, Synopsys primarily leverages the company's digital design and verification series to implement the ARC/ARC-V cores, and provides a Fusion Quick Start Kit for high-performance ARC/ARC-V cores, while also offering design services to customers.
To accelerate software development, the ARC-V processor is supported by Synopsys' MetaWare development tool kit. In addition, Synopsys' extensive EDA tool suite provides an out-of-the-box development and verification environment to help design and fully verify RISC-V-based SoCs. Currently, Synopsys has an increasing number of ARC-V customers, and once customers choose the processor IP, Synopsys can provide customers with a rich set of EDA tools, processes, and IP.
Despite having a strong competitive advantage, Synopsys always adheres to open cooperation and is closely connected with the entire processor ecosystem. In terms of RISC-V, Synopsys collaborates extensively with major customers, RISC-V core providers, foundries, and universities. Synopsys has also built customized processes to help RISC-V designs be efficiently implemented and verified. In addition, Synopsys has partnered with SiFive to launch the Fusion QuickStart Kit (QIK), providing a convenient development platform for RISC-V developers, which is now available.
AI Assists in Optimizing High-Performance RISC-V CPU Cores
Artificial intelligence (AI) is permeating every aspect of our lives with unstoppable momentum, and processor design is no exception. In the field of CPU core optimization for the RISC-V architecture, AI is playing an increasingly important role, helping chip designers achieve performance and power consumption goals more quickly and effectively.
Synopsys' DSO.ai AI-driven RISC-V reference process is a great example. In a case of a "big core" based on the RISC-V architecture and designed for data center applications, the role of AI is greatly demonstrated. The single-core size of this RISC-V CPU is 426um x 255um, with a target process technology of 5nm. The initial benchmark design operates at a frequency of 1.75GHz with a power consumption of 29.8mW, representing the out-of-the-box performance of the RISC-V reference process.
The expected target of the design is to achieve 1.95GHz at a power consumption of 30mW. According to traditional methods, it is estimated that two professional engineers would need about a month to complete the optimization. However, by applying Synopsys' DSO.ai AI-driven RISC-V reference process, the goal was achieved in just two days, after 90 software runs, without any human intervention, while also achieving the expected area target.
This is the future of processor design and represents a significant shift in the paradigm of processor design! AI technology demonstrates astonishing optimization capabilities, significantly improving design efficiency and shortening development cycles, helping chip designers quickly achieve performance and power consumption goals.Summary
It's not just RISC-V; Synopsys also has extensive support for Arm processors. Arm has always been a strong partner of Synopsys. The collaboration between Synopsys and Arm mainly revolves around the following aspects: in-depth cooperation on advanced nodes below 2nm; providing the latest core Fusion QuickStart Kits and verification support documents; and tuning the core to achieve the best out-of-the-box PPA (Power, Performance, and Area).
In summary, Synopsys' strategic move into the RISC-V market is in line with market trends and expands new business growth points. Although the RISC-V market has certain challenges, it also contains huge opportunities. With its strong technical strength and rich experience in the field of processors, Synopsys is expected to succeed in the RISC-V market and contribute to the prosperity and development of the RISC-V ecosystem.
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