Undoubtedly, in the fields of chip design, upstream EDA, IP, and equipment, the United States is in a league of its own, leveraging its chip dominance to wield a sickle around the world.
However, over the past few decades, the United States' position in the semiconductor manufacturing industry has been on a continuous decline. In 1990, the U.S. controlled 37% of the global semiconductor manufacturing business. Today, this share has dropped to less than 10%.
Amid the increasingly prominent and important trend of supply chain issues, chip manufacturing and capacity have become the new targets that the industry is eager to pursue. Among them, by introducing the "Chips and Science Act," the United States has expressed its desire and ambition to bring semiconductor wafer manufacturing facilities to the country.
Advertisement
With major wafer manufacturers such as TSMC, Intel, and Samsung all announcing plans to build factories in the U.S., the U.S. Department of Commerce has set a new goal for the chip industry: to have advanced chips produced in the U.S. account for 20% of the global market share by 2030.
On the other hand, in recent years, the slowdown of Moore's Law has led to a sharp increase in the marginal cost of chip performance growth. At the same time, the demand for AI, high-performance computing chips, and other areas is increasingly rising, and advanced packaging has become another new trend that the industry is chasing.
Semiconductor industry leaders have invested heavily in the field of advanced packaging, laying the foundation for the development of multi-chip packaging technology. According to data forecasts from Yole Group, the global market size of advanced packaging will grow from $44.3 billion in 2022 to $78.6 billion in 2028, with a compound annual growth rate (CAGR) of 10.6%.
Against this background and trend, in order to fully ensure the security of the entire semiconductor supply chain, the development of advanced packaging has also become a new focus for the United States.
Advanced packaging, how is the United States making efforts?Policy and Funding Guidance
The United States "CHIPS and Science Act" was enacted in August 2022, with plans to allocate more than $52.7 billion in funds to support the research and development, manufacturing, and workforce development of American semiconductors. In recent years, the U.S. government has provided preferential policies and investment subsidies to more than ten related enterprises, including GlobalWafers America, Rogue Valley Microdevices, Entegris, Micron, Samsung, TSMC, Intel, GlobalFoundries, Microchip Technology, Amkor Technology, etc.
In addition to this, the United States has also set up special funds to increase investment in the packaging field.
On November 20, 2023, the National Institute of Standards and Technology (NIST) of the U.S. Department of Commerce released the "National Advanced Packaging Manufacturing Program Vision" report. The U.S. government emphasized in the new strategy of the semiconductor industry that advanced packaging technology is one of the key technologies for manufacturing the most advanced semiconductors. Strengthening the capabilities of American advanced packaging technology is crucial for the competitiveness of the U.S. semiconductor industry and its position in the global market.
The U.S. Department of Commerce will invest about $3 billion to promote the National Advanced Packaging Manufacturing Program (NAPMP) and will prioritize investment in six key areas:
Materials and Substrates
Equipment, Tools, and Processes
Power Supply and Thermal Management
Optoelectronics and Connectors
Chiplet EcosystemEDA and Collaborative Design
The green sections are technology-oriented investment projects, while the blue ones are ecology-oriented investment projects.
It is reported that the NAPMP plan is expected to announce its first funding opportunity in 2024, targeting the fields of materials and substrates. In addition, to ensure the smooth operation of new technologies and tools, the NAPMP plan will also include personnel training programs, dedicated to cultivating a sufficient number of professionals for new processes and tools.
Through investments in the above six areas, the NAPM project hopes to develop a series of advanced packaging technologies, equipment, materials, and processes to enhance the semiconductor manufacturing and testing capabilities in the United States and create more semiconductor job opportunities.
At the same time, as one of the four major R&D plans of CHIPS for America, the NAPMP aims to jointly establish the necessary innovation ecosystem to ensure that the R&D of semiconductor manufacturing facilities in the United States produces the world's most advanced and cutting-edge technologies.
Recently, the U.S. Department of Commerce has issued a new Notice of Intent (NOI), announcing an investment of $1.6 billion to support the development of chip packaging technology in the United States, in order to establish and accelerate domestic semiconductor advanced packaging capacity. As shown in the U.S. NAPMP vision, the "Chip Act" is expected to provide up to $1.6 billion in funding for innovation in five R&D areas. After each project applicant submits a declaration, they will compete for funding support, with the maximum government funding for a single project capped at $150 million.
The New York Times pointed out that the United States' dependence on overseas in the field of chip packaging is greater than its dependence on overseas in chip manufacturing. At present, the global chip packaging industry is mainly concentrated in Asia, especially in Taiwan and South Korea, while the United States only accounts for 3% of the global total chip packaging.
The $1.6 billion in chip packaging support funds announced this time is part of the newly established NAPMP project of the U.S. government, which will have a total fund of about $3 billion.
Previously, the U.S. government has provided preferential policies to related companies, including Intel, SK Hynix, Amkor, and Samsung Electronics, to attract them to establish chip packaging factories in the United States. The U.S. Deputy Secretary of Commerce, Locascio, confidently declared that within 10 years, the United States will be able to build a domestic chip packaging industry, and at that time, cutting-edge chips produced by the United States and overseas can be packaged in the United States.Industry Chain Manufacturers Make a Strong Entry
● Amkor, the Sole Survivor of U.S. OSAT
Currently, there are 25 OSAT suppliers in the United States, but not all can provide advanced packaging capabilities. Among them, the most famous OSAT supplier in the United States is Amkor.
At the end of November 2023, Amkor announced an investment of about 2 billion U.S. dollars to build an advanced packaging and testing facility in Arizona, USA, to achieve a resilient semiconductor supply chain. Once completed, it will be the largest advanced packaging facility for OSAT in the United States.
Amkor stated that this advanced packaging and testing facility will provide a complete end-to-end advanced packaging for the world's most advanced semiconductors, for high-performance computing, artificial intelligence, communication, and automotive end markets. Moreover, its advanced packaging technologies such as 2.5D technology and other next-generation technologies will be adopted.
Amkor's President and CEO, Giel Rutten, said, "The expansion of the U.S. semiconductor supply chain is underway. As the largest advanced packaging company in the United States, we are delighted to play a leading role in enhancing the U.S. advanced packaging capabilities and to be a part of a strong U.S. semiconductor ecosystem."
On July 26, the U.S. Department of Commerce announced that it had signed a non-binding preliminary memorandum of understanding (PMT) with Amkor. The U.S. government will grant Amkor up to 400 million U.S. dollars in direct funding and 200 million U.S. dollars in loans according to the "Chips and Science Act." This proposed funding will support Amkor's investment of about 2 billion U.S. dollars and 2,000 jobs in a greenfield project in Peoria, Arizona.
It is understood that the initial construction phase of Amkor's factory in Peoria, Arizona, is expected to last 3 years, that is, to be operational in 2027. Amkor's factory is adjacent to Intel Foundry and TSMC's wafer fabs in Arizona. Chip design companies using the above wafer foundry services can package their chips in that state.
It is reported that Apple will be the first and largest customer of this facility. Apple has publicly recognized Amkor's packaging facility in Arizona and stated that it will use TSMC and Amkor's services in Arizona to manufacture and package its chips.Essentially, Amkor's facilities have established a robust domestic semiconductor supply chain and positioned Amkor as a key partner for fabless chip design companies and wafer foundries.
Moreover, Amkor has been expanding its investment in the packaging market in recent years and has further enriched the company's product line and technical capabilities through the acquisition of J-Devices and NANIUM S.A.
● Intel, a leader in advanced packaging
As a domestic IDM and wafer foundry giant in the United States, Intel is also actively deploying advanced packaging.
Through years of technological exploration, Intel has successively introduced various advanced packaging technologies such as EMIB, Foveros, and Co-EMIB, aiming to achieve the goal of doubling interconnect bandwidth and halving power consumption through various heterogeneous integration forms such as 2.5D, 3D, and embedded.
EMIB is Intel's attempt in 2.5D IC, and its full name is "Embedded Multi-Die Interconnect Bridge." It does not introduce an additional silicon interposer but only adds a silicon bridge layer at the edge connection of two bare chips and re-customizes the I/O pins on the edge of the bare chips to match the bridge standard.
In December 2018, Intel demonstrated a new 3D packaging technology called "Foveros," which is another leap in Intel's advanced packaging technology following the introduction of the groundbreaking EMIB packaging technology in 2018.
Intel first introduced the concept of 3D stacking in the Foveros technology, which can achieve the stacking of logic chips on logic chips, interconnecting horizontally and vertically, and further reducing the bump pitch to 50-25um.
Foveros can integrate chips with different processes, structures, and purposes, thereby assembling more computing circuits onto a single chip, achieving high performance, high density, and low power consumption. This technology offers great flexibility, allowing designers to "mix and match" different technical patent modules, various memory chips, and I/O configurations in new product forms, and enabling products to be broken down into smaller "chip combinations."It can be considered that Foveros has paved the way for devices and systems that integrate high-performance, high-density, and low-power silicon process technologies.
In 2019, Intel once again introduced a new packaging technology called Co-EMIB, which is an innovative application that combines EMIB and Foveros technologies. Co-EMIB allows two or more Foveros components to be interconnected, and it essentially achieves the performance level of a single chip. Designers can also use Co-EMIB technology to achieve high bandwidth and low power consumption connections for simulators, memory, and other modules.
Intel Advanced Packaging Technology Roadmap
From Intel's advanced packaging technology development roadmap, it can be seen that its advanced packaging mainly focuses on three aspects: interconnect density, power efficiency, and scalability. Among them, Foveros and hybrid bonding technology mainly focus on power efficiency and interconnect density, while Co-EMIB and ODI technologies reflect the scalability of integration.
From Foveros to hybrid bonding technology, Intel gradually achieves smaller bump pitches, enabling the system to have higher current load capacity and better thermal performance. In the future, Intel will continue to strive to maximize functionality per cubic millimeter.
Last May, Intel released a blueprint for advanced packaging technology, planning to transform traditional substrates into more advanced glass substrates.
Reports indicate that Intel's move is an attempt to switch materials to achieve high-performance semiconductors beyond the limitations of existing plastic substrates.
With the popularization of 3D packaging, thickness has become a more concerned factor. The key to improving performance by vertically stacking semiconductors is to reduce the thickness of the substrate. Glass substrates have a flat surface and can be made very thin, and their thickness can be reduced by about half compared to ABF plastic. Thinning can improve signal transmission speed and power efficiency. Therefore, Intel is expected to improve the 3D packaging structure through glass substrates.Additionally, with the surge in computing demand triggered by ChatGPT, the CPO (Co-Packaged Optics) technology in silicon photonic modules, as a key technology to optimize the cost of computing power, has tremendous development potential. Intel is also positioning itself in this area.
Compared to traditional optical modules, CPO can reduce power consumption by about 50% at the same data transmission rate, effectively addressing the issue of electrical interconnects being limited by energy consumption in high-speed, high-density interconnection transmission scenarios, making it difficult to significantly enhance data transmission capabilities. At the same time, compared to traditional photonic technologies based on III-V materials, the silicon photonic technology mainly used by CPO has advantages in cost and size.
For a long time, Intel's packaging technology has been mainly used in its own products, having a relatively small impact on the market. With the introduction of Intel's IDM 2.0 development strategy, foundry business has become an important transformation project for Intel. In addition to manufacturing for fabless semiconductor companies such as Qualcomm, its packaging technology is also a key focus of Intel's sales efforts. Intel stated that customers can choose to have foundry manufacturing done by TSMC, GF, and others, and then use Intel's technology for packaging and testing. This model will bring more flexible product manufacturing methods to customers.
Intel emphasized that it has already been in talks with customers of the top 10 global chip packaging factories and has gained favor from industry players such as Cisco and AWS.
It is reported that Intel is actively deploying advanced packaging technology and capacity, not only in New Mexico and Arizona in the United States but also expanding its new plant in Penang, Malaysia, and its factory construction plan in Poland, further consolidating its position in the global advanced packaging field.
● Actively attracting foreign companies to the United States
At the same time, the United States' subsidy policy has not only attracted the active participation of domestic companies but also the attention and investment of international companies. Under the incentive of the "CHIPS and Science Act," several foreign companies have planned to land packaging projects in the United States. For example, South Korea's chip manufacturer SK Hynix plans to invest $15 billion in the United States to establish advanced packaging facilities; Samsung is investing $40 billion in chip manufacturing in Texas, including a plan to build an advanced packaging factory. Samsung's new factory in Texas will have 2.5D and HBM packaging capabilities; TSMC is also negotiating with Arizona, possibly building an advanced packaging factory in the state.
● EDA tool suppliers
Chip design is a highly complex and long-term process. Without the help of EDA tools, it is almost impossible to create chip designs. EDA tools are also very important for advanced packaging operations, and various types of EDA tools are used to model and analyze the reliability of packaging, the design of packaging antennas, and many other aspects of packaging design.
Companies such as Synopsys, Cadence, and Ansys (acquired by Synopsys) provide extended EDA tool options for chip design and packaging. For example, Cadence recently began to provide its 3DIC SiP simulation tool suite; with Ansys, antennas can be modeled and designed in AiP. Therefore, the main EDA tool companies in the United States provide the EDA tools needed for designing advanced packaging.In addition, Synopsys recently announced further expansion of its cooperation with TSMC, with both parties working together to continuously optimize multi-die system design through a comprehensive solution that supports the latest 3Dblox 2.0 standard and TSMC's 3DFabric™ technology.
Synopsys' multi-die system solution includes the "from architecture exploration to sign-off" unified design platform 3DIC Compiler, which can provide industry-leading design efficiency to meet the capacity and performance requirements of chips. In addition, Synopsys UCIe IP has also achieved its first successful pass through silicon on TSMC's leading N3E advanced process, achieving high-speed seamless interconnection between dies.
At the same time, Synopsys and Ansys continue to cooperate, integrating Synopsys 3DIC Compiler and Ansys multi-physics analysis technology to provide system-level sign-off accuracy. Synopsys 3DIC Compiler can also interoperate with Synopsys test products to ensure mass testing and quality.
In addition, the Synopsys 3DIO platform provides flexibility, scalability, and optimal performance.
It is understood that the Synopsys 3DIO platform is specifically adjusted for multi-chip heterogeneous integration, providing multi-functional solutions to achieve the best balance of power, performance, and area (PPA) in 3D stacking to meet emerging packaging needs. In addition, the platform can also accelerate timing convergence, which is a key challenge in chip-to-chip integration.
The Synopsys 3DIO platform provides customers with multi-functional solutions to achieve adjustable integrated multi-chip design structures. The optimal area of Synopsys 3DIO platform is carefully designed to adapt to BUMPs, providing significant advantages in implementation and signal wiring. In 3D stacking technology, the source-synchronous clock design for signal transmission can help customers achieve lower BER and simplify timing convergence. The Synopsys 3DIO platform is tailored for multi-chip integration, enabling customers to create efficient chip designs and accelerate time to market, using the Synopsys 3DIC compiler to accelerate integration and provide optimized PPA for a given technology.
In addition to the 3DIO platform, Synopsys' multi-chip solution also includes UCIe IP and HBM3 IP, etc.
● Device VendorsDifferent stages of packaging manufacturing use various types of equipment, such as cutting, wire bonding, microbump, and hybrid bonding. For example, in WLP, wafers need to be cut, and then a Redistribution Layer (RDL) is formed on the top of the wafer. This step requires traditional photolithography equipment used for chip manufacturing; flip-chip bonding equipment directly connects the IC chip to the substrate or PCB by precisely positioning and bonding the solder bumps on the chip to the corresponding pads on the substrate, thus achieving high-density interconnection. In addition, various testing and inspection equipment are used to verify the function and quality of the packaged IC, including Automatic Optical Inspection (AOI) systems, X-ray inspection machines, electrical testers, and other specialized test tools.
In the field of equipment, Applied Materials and Lam Research are typical examples of suppliers of semiconductor industry and advanced packaging equipment in the United States. In addition, KLA, Onto Innovation, Nordson, Thermo Fisher Scientific, and Bruker also provide various equipment to meet measurement needs. American companies provide the necessary inspection and measurement tools for each stage of the manufacturing process.
● Material Suppliers
Advanced packaging of semiconductors requires complex manufacturing and process flows, such as cutting wafers, placing them into molds, wire bonding, stacking, or packaging chips. Different raw materials are needed at different stages of the process flow, such as dielectric materials, lead frames, adhesives, sealants, and molding compounds, which are the most critical materials for packaging chips.
From the supply chain perspective, although the United States has suppliers of raw materials needed for packaging, most materials are supplied by Japan, mainland China, and Taiwan. The United States currently has a 10% market share of semiconductor materials, which may bring vulnerabilities to the semiconductor supply chain, including advanced packaging. To support advanced packaging manufacturing, the United States is further strengthening investment to ensure the security of the raw material supply chain.
For example, in November last year, Resonac, a Japanese semiconductor material manufacturer, announced that it would establish an advanced semiconductor packaging and material R&D center in Silicon Valley, USA. Resonac, formerly known as Showa Denko, is a leading manufacturer of packaging materials such as thin films, and plans to start operations at the new center in 2025.
In May of this year, the US Department of Commerce stated that it plans to grant Absolics (a US subsidiary of SKC under the Korean SK Group) $75 million to build a 120,000 square foot factory in Georgia to supply advanced materials to the US semiconductor industry. The award will also support 1,000 construction jobs and 200 manufacturing and R&D jobs in Covington, Georgia. Absolics' glass substrates allow processing chips and storage chips to be packaged into a single device, achieving faster and more efficient computing.
In addition, there is not enough public information on whether the under-construction wafer fabs or foundries also plan to integrate advanced packaging businesses. Therefore, it is necessary to ensure that IDMs and foundries plan to develop advanced packaging businesses, and to encourage third-party OSAT companies to develop capabilities, capacity, and preparedness in the United States to meet future demand for advanced packaging services.
Regarding the impact and enlightenment of the United States' development plan for advanced packaging manufacturing, the author believes:1) Aimed at strengthening the competitive advantage of American products and technologies: According to the plan's main investment areas, future subsidies will be provided for advanced packaging products manufactured in the United States, reducing their R&D, manufacturing, and production costs, and enhancing their product competitiveness.
2) The United States has not slowed down the pace of "derisking" in key areas: When announcing the NAPMP plan, the U.S. Department of Commerce stated, "Manufacturing chips in the United States and then shipping them overseas for packaging poses risks to the supply chain and national security, which is unacceptable." Therefore, under the incentives of the U.S. Chip Act, many foreign companies have already planned to land their packaging projects in the United States. The industrial alliance system built around this plan will have greater say in the future, building its own industrial ecological barriers.
In conclusion, since the end of last year, the U.S. government has initiated the allocation of funds under the "Chips and Science Act," providing $52.7 billion for the research and development, manufacturing, and workforce development of American semiconductors. In addition, the plan also provides a 25% investment tax credit for capital expenditures in the manufacturing of semiconductors and related equipment.
With the support of policies and funds, a large number of semiconductor manufacturing business restructuring activities have been stimulated. The construction of semiconductor manufacturing facilities is booming in the United States, promoting the scale and capacity of local chip production.
Correspondingly, if the United States cannot establish a solid and strong advanced packaging ecosystem, the chips produced by new production facilities across the country will have to be shipped overseas for packaging, as in the past. The above-mentioned practice poses risks to the supply chain and national security, which is also unacceptable to the United States.
Therefore, the United States has also attached great importance to the manufacturing capabilities of advanced packaging.
However, looking at the current state of the industry, the participants and business models in the advanced packaging market are continuously expanding and evolving, and competition in this field has become more intense, with other countries also actively developing the industry. The United States' large-scale investment and active layout in the field of advanced packaging this time may also easily trigger other countries and regions to increase their investment in the advanced packaging industry, and the U.S. advanced packaging industry may also face new competitive pressures from other countries.
On the other hand, despite the continuous increase in investment in the United States in the fields of wafer manufacturing and advanced packaging, high labor costs and a shortage of industry talent remain a challenge. According to industry experts, the development of the U.S. semiconductor industry's workforce has encountered some key challenges, such as students' lack of interest in hardware electronic technology, outdated courses that ignore modern semiconductor technology, talent retention issues, and aging of teachers and infrastructure. Addressing these obstacles is crucial for promoting the future development and innovation of the industry.Therefore, in order to maintain competitiveness in the talent war, the U.S. government and businesses are exploring strategies such as retraining, automation, and expanding talent pipelines, attempting to invest and encourage the younger generation at the national level to meet the needs of the wafer manufacturing, advanced packaging, and other industries, and to sustain future growth.
For example, the "CHIPS and Science Act" has stimulated significant activities in the field of education, with more than 50 community colleges announcing the establishment or expansion of semiconductor-related courses. Major chip manufacturers such as Intel, TSMC, Samsung, and Micron have allocated funds specifically for workforce development as part of their talent cultivation contributions.
Overall, the U.S. is adopting an ambitious "all-round" action plan, focusing on multiple aspects such as wafer manufacturing, advanced packaging, and talent training, and is committed to realizing its ambition to revitalize the semiconductor industry.
Shenzhen High-quality Development and New Structure Research Institute: Analysis of the U.S. National Chip Advanced Packaging Manufacturing Plan;
Frontiers of Strategic Technology: The U.S. Releases the "National Advanced Packaging Manufacturing Plan Vision" Report;
Comments